simplify/cleanup code + bugfixes

- x86_64 seL4_TCBOject size is implemented

- ioapic level_triggered and active_low were incorrect
parent d35e18f7
Pipeline #464 canceled with stage
......@@ -19,11 +19,14 @@ pub trait ObjectAllocator {
/// Otherwise, allocate a slot in this thread's CSpace.
fn allocate_slot(&self) -> Option<SlotRef>;
/// Mark a slot unused and available for allocation.
fn free_slot(&self, slot: SlotRef) -> Result<(), Self::SlotFreeError>;
/// Allocate an object, storing the capability into the specified slot.
fn allocate_object<T: Allocatable>(&self, dest: SlotRef) -> Result<Option<T>, Self::ObjectAllocError>;
fn allocate_object<T: Allocatable>(&self, dest: SlotRef)
-> Result<Option<T>, Self::ObjectAllocError>;
/// Free an object, deleting it (thus removing it from the capability derivation tree) and
/// return the memory for use by the allocator.
fn free_object<T: Allocatable>(&self, obj: T) -> Result<(), Self::ObjectFreeError>;
......
......@@ -8,28 +8,27 @@
// according to those terms.
use sel4_sys::*;
use ToCap;
cap_wrapper_inner!{
#[doc = "Authority to allocate ASID pools"]
:ASIDControl
#[doc = "Authority to create page directories"]
:ASIDPool
}
cap_wrapper!{ ()
/// Authority to allocate ASID pools
ASIDControl,
/// Authority to create page directories
ASIDPool,
cap_wrapper!{
#[doc = "A 4K page of physical memory mapped into a page table"]
:SmallPage seL4_ARM_SmallPageObject |_| 1 << 10
#[doc = "A 64K page of physical memory mapped into a page table"]
:LargePage seL4_ARM_LargePageObject |_| 1 << 16
#[doc = "A 1M page of physical memory mapped into a page directory"]
:Section seL4_ARM_SectionObject |_| 1 << 20
#[doc = "A 16M page of physical memory mapped into a page directory"]
:SuperSection seL4_ARM_SuperSectionObject |_| 1 << 24
#[doc = "A page table, which can have pages mapped into it"]
:PageTable seL4_ARM_PageTableObject |_| 1 << 10
#[doc = "A page directory, which holds page tables or sections and forms the root of the vspace"]
:PageDirectory seL4_ARM_PageDirectoryObject |_| 1 << 14
/// A 4K page of physical memory mapped into a page table
SmallPage = seL4_ARM_SmallPageObject |_| 1 << 10,
/// A 64K page of physical memory mapped into a page table
LargePage = seL4_ARM_LargePageObject |_| 1 << 16,
/// A 1M page of physical memory mapped into a page directory
Section = seL4_ARM_SectionObject |_| 1 << 20,
/// A 16M page of physical memory mapped into a page directory
SuperSection = seL4_ARM_SuperSectionObject |_| 1 << 24,
/// A page table, which can have pages mapped into it
PageTable = seL4_ARM_PageTableObject |_| 1 << 10,
/// A page directory, which holds page tables or sections and forms the root of the vspace
PageDirectory = seL4_ARM_PageDirectoryObject |_| 1 << 14,
}
impl ASIDControl {
......@@ -39,7 +38,13 @@ impl ASIDControl {
/// `untyped` must be 4KiB.
#[inline(always)]
pub fn make_pool(&self, untyped: SmallPage, dest: ::SlotRef) -> ::Result {
errcheck!(seL4_ARM_ASIDControl_MakePool(self.cptr, untyped.to_cap(), dest.root.to_cap(), dest.cptr, dest.depth));
unsafe_as_result!(seL4_ARM_ASIDControl_MakePool(
self.cptr,
untyped.to_cap(),
dest.root.to_cap(),
dest.cptr,
dest.depth,
))
}
}
......@@ -47,7 +52,7 @@ impl ASIDPool {
/// Assign a page directory to this ASID pool.
#[inline(always)]
pub fn assign(&self, vroot: PageDirectory) -> ::Result {
errcheck!(seL4_ARM_ASIDPool_Assign(self.cptr, vroot.to_cap()));
unsafe_as_result!(seL4_ARM_ASIDPool_Assign(self.cptr, vroot.to_cap()))
}
}
......@@ -56,20 +61,22 @@ macro_rules! page_impls {
impl $name {
/// Map this page into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights, attr: seL4_ARM_VMAttributes) -> ::Result {
errcheck!(seL4_ARM_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr));
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights,
attr: seL4_ARM_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_ARM_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr))
}
/// Remap this page, possibly changing rights or attribute but not address.
#[inline(always)]
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_ARM_VMAttributes) -> ::Result {
errcheck!(seL4_ARM_Page_Remap(self.cptr, pd.to_cap(), rights, attr));
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights,
attr: seL4_ARM_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_ARM_Page_Remap(self.cptr, pd.to_cap(), rights, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_ARM_Page_Unmap(self.cptr));
unsafe_as_result!(seL4_ARM_Page_Unmap(self.cptr))
}
/// Get the physical address of the underlying frame.
......@@ -96,12 +103,12 @@ impl PageTable {
/// Map this page table into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, attr: seL4_ARM_VMAttributes) -> ::Result {
errcheck!(seL4_ARM_PageTable_Map(self.cptr, pd.to_cap(), addr, attr));
unsafe_as_result!(seL4_ARM_PageTable_Map(self.cptr, pd.to_cap(), addr, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_ARM_PageTable_Unmap(self.cptr));
unsafe_as_result!(seL4_ARM_PageTable_Unmap(self.cptr))
}
}
// Copyright (c) 2015 The Robigalia Project Developers
// Licensed under the Apache License, Version 2.0
// <LICENSE-APACHE or
// http://www.apache.org/licenses/LICENSE-2.0> or the MIT
// license <LICENSE-MIT or http://opensource.org/licenses/MIT>,
// at your option. All files in the project carrying such
// notice may not be copied, modified, or distributed except
// according to those terms.
#[cfg(target_arch = "x86")]
mod x86;
#[cfg(target_arch = "x86")]
pub use self::x86::*;
#[cfg(target_arch = "x86_64")]
mod x86_64;
#[cfg(target_arch = "x86_64")]
pub use self::x86_64::*;
#[cfg(all(target_arch = "arm", target_pointer_width = "32"))]
mod arm;
#[cfg(all(target_arch = "arm", target_pointer_width = "32"))]
pub use self::arm::*;
......@@ -8,29 +8,29 @@
// according to those terms.
use sel4_sys::*;
use ToCap;
cap_wrapper_inner!{
#[doc = "Authority to create ASID pools"]
:ASIDControl
#[doc = "Authority to create page directories"]
:ASIDPool
#[doc = "Authority to use port-IO"]
:IOPort
#[doc = "Authority to map IO page tables into a device's address space"]
:IOSpace
}
cap_wrapper!{
#[doc = "A page table for the IOMMU"]
:IOPageTable seL4_X86_IOPageTableObject |_| 1 << 10
#[doc = "A page of physical memory that can be mapped into a vspace"]
:Page seL4_X86_4K |_| 1 << 10
#[doc = "A 'large page' (4MiB) for use with PAE"]
:LargePage seL4_X86_LargePageObject |_| 1 << 22
#[doc = "A page table, which can have pages mapped into it"]
:PageTable seL4_X86_PageTableObject |_| 1 << 10
#[doc = "A page directory, which holds page tables and forms the root of the vspace"]
:PageDirectory seL4_X86_PageDirectoryObject |_| 1 << 10
cap_wrapper!{ ()
/// Authority to create ASID pools
ASIDControl,
/// Authority to create page directories
ASIDPool,
/// Authority to use port-IO
IOPort,
/// Authority to map IO page tables into a device's address space
IOSpace,
/// A page table for the IOMMU
IOPageTable = seL4_X86_IOPageTableObject |_| 1 << 10,
/// A page of physical memory that can be mapped into a vspace
Page = seL4_X86_4K |_| 1 << 10,
/// A 'large page' (4MiB) for use with PAE
LargePage = seL4_X86_LargePageObject |_| 1 << 22,
/// A page table, which can have pages mapped into it
PageTable = seL4_X86_PageTableObject |_| 1 << 10,
/// A page directory, which holds page tables and forms the root of the vspace
PageDirectory = seL4_X86_PageDirectoryObject |_| 1 << 10,
}
impl ASIDControl {
......@@ -40,7 +40,13 @@ impl ASIDControl {
/// `untyped` must be 4KiB.
#[inline(always)]
pub fn make_pool(&self, untyped: Page, dest: ::SlotRef) -> ::Result {
errcheck!(seL4_X86_ASIDControl_MakePool(self.cptr, untyped.to_cap(), dest.root.to_cap(), dest.cptr, dest.depth));
unsafe_as_result!(seL4_X86_ASIDControl_MakePool(
self.cptr,
untyped.to_cap(),
dest.root.to_cap(),
dest.cptr,
dest.depth,
))
}
}
......@@ -48,7 +54,7 @@ impl ASIDPool {
/// Assign a page directory to this ASID pool.
#[inline(always)]
pub fn assign(&self, vroot: PageDirectory) -> ::Result {
errcheck!(seL4_X86_ASIDPool_Assign(self.cptr, vroot.to_cap()));
unsafe_as_result!(seL4_X86_ASIDPool_Assign(self.cptr, vroot.to_cap()))
}
}
......@@ -89,19 +95,19 @@ impl IOPort {
/// Write 8-bit `value` to the given port.
#[inline(always)]
pub fn write8(&self, port: u16, value: u8) -> ::Result {
errcheck!(seL4_X86_IOPort_Out8(self.cptr, port as seL4_Word, value as seL4_Word));
unsafe_as_result!(seL4_X86_IOPort_Out8(self.cptr, port as seL4_Word, value as seL4_Word))
}
/// Write 16-bit `value` to the given port.
#[inline(always)]
pub fn write16(&self, port: u16, value: u16) -> ::Result {
errcheck!(seL4_X86_IOPort_Out16(self.cptr, port as seL4_Word, value as seL4_Word));
unsafe_as_result!(seL4_X86_IOPort_Out16(self.cptr, port as seL4_Word, value as seL4_Word))
}
/// Write 32-bit `value` to the given port.
#[inline(always)]
pub fn write32(&self, port: u16, value: u32) -> ::Result {
errcheck!(seL4_X86_IOPort_Out32(self.cptr, port as seL4_Word, value as seL4_Word));
unsafe_as_result!(seL4_X86_IOPort_Out32(self.cptr, port as seL4_Word, value as seL4_Word))
}
}
......@@ -109,7 +115,7 @@ impl IOPageTable {
/// Map this page table into an IOSpace at `addr`
#[inline(always)]
pub fn map(&self, iospace: IOSpace, addr: seL4_Word) -> ::Result {
errcheck!(seL4_X86_IOPageTable_Map(self.cptr, iospace.to_cap(), addr));
unsafe_as_result!(seL4_X86_IOPageTable_Map(self.cptr, iospace.to_cap(), addr))
}
}
......@@ -118,25 +124,27 @@ impl Page {
/// Map this page into an IOSpace with `rights` at `addr`.
#[inline(always)]
pub fn map_io(&self, iospace: IOSpace, rights: seL4_CapRights, addr: seL4_Word) -> ::Result {
errcheck!(seL4_X86_Page_MapIO(self.cptr, iospace.to_cap(), rights, addr));
unsafe_as_result!(seL4_X86_Page_MapIO(self.cptr, iospace.to_cap(), rights, addr))
}
/// Map this page into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr));
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights,
attr: seL4_X86_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_X86_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr))
}
/// Remap this page, possibly changing rights or attribute but not address.
#[inline(always)]
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_Page_Remap(self.cptr, pd.to_cap(), rights, attr));
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_X86_VMAttributes)
-> ::Result {
unsafe_as_result!(seL4_X86_Page_Remap(self.cptr, pd.to_cap(), rights, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_Page_Unmap(self.cptr));
unsafe_as_result!(seL4_X86_Page_Unmap(self.cptr))
}
/// Get the physical address of the underlying frame.
......@@ -157,13 +165,13 @@ impl PageTable {
/// Map this page table into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_PageTable_Map(self.cptr, pd.to_cap(), addr, attr));
unsafe_as_result!(seL4_X86_PageTable_Map(self.cptr, pd.to_cap(), addr, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_PageTable_Unmap(self.cptr));
unsafe_as_result!(seL4_X86_PageTable_Unmap(self.cptr))
}
}
......@@ -173,7 +181,7 @@ impl PageDirectory {
/// Returns (accessed, dirty).
#[inline(always)]
pub fn get_status(&self, vaddr: usize) -> Result<(bool, bool), ::Error> {
let res = unsafe { seL4_X86_PageDirectory_GetStatusBits(self.cptr, vaddr as seL4_Word) };
let res = unsafe { seL4_X86_PageDirectory_GetStatusBits(self.cptr, vaddr) };
if res.error == 0 {
unsafe {
let buf = seL4_GetIPCBuffer();
......@@ -196,8 +204,19 @@ impl ::irq::IRQControl {
///
/// `vector` is the CPU vector the interrupt will be delivered to.
#[inline(always)]
pub fn get_msi(&self, slotref: ::SlotRef, pci_bus: seL4_Word, pci_dev: seL4_Word, pci_func: seL4_Word, handle: seL4_Word, vector: seL4_Word) -> ::Result {
errcheck!(seL4_IRQControl_GetMSI(self.to_cap(), slotref.root.to_cap(), slotref.cptr, slotref.depth as seL4_Word, pci_bus, pci_dev, pci_func, handle, vector));
pub fn get_msi(&self, slotref: ::SlotRef, pci_bus: seL4_Word, pci_dev: seL4_Word,
pci_func: seL4_Word, handle: seL4_Word, vector: seL4_Word) -> ::Result {
unsafe_as_result!(seL4_IRQControl_GetMSI(
self.to_cap(),
slotref.root.to_cap(),
slotref.cptr,
slotref.depth as seL4_Word,
pci_bus,
pci_dev,
pci_func,
handle,
vector,
))
}
/// Create an IRQHandler capability for an interrupt from an IOAPIC.
......@@ -212,7 +231,19 @@ impl ::irq::IRQControl {
///
/// `vector` is the CPU vector the interrupt will be delivered on.
#[inline(always)]
pub fn get_ioapic(&self, slotref: ::SlotRef, ioapic: seL4_Word, pin: seL4_Word, level_triggered: bool, active_low: bool, vector: seL4_Word) -> ::Result {
errcheck!(seL4_IRQControl_GetIOAPIC(self.to_cap(), slotref.root.to_cap(), slotref.cptr, slotref.depth as seL4_Word, ioapic, pin, if level_triggered { 0 } else { 1 }, if active_low { 0 } else { 1 }, vector));
pub fn get_ioapic(&self, slotref: ::SlotRef, ioapic: seL4_Word, pin: seL4_Word,
level_triggered: bool, active_low: bool, vector: seL4_Word)
-> ::Result {
unsafe_as_result!(seL4_IRQControl_GetIOAPIC(
self.to_cap(),
slotref.root.to_cap(),
slotref.cptr,
slotref.depth as seL4_Word,
ioapic,
pin,
level_triggered as usize,
active_low as usize,
vector,
))
}
}
This diff is collapsed.
......@@ -9,9 +9,18 @@
//! Dealing with CNodes
use sel4_sys::*;
use sel4_sys::{seL4_CNode_CancelBadgedSends, seL4_CNode_Copy, seL4_CNode_Delete, seL4_CNode_Mint,
seL4_CNode_Move, seL4_CNode_Mutate, seL4_CNode_Revoke, seL4_CNode_Rotate,
seL4_CNode_SaveCaller, seL4_CPtr, seL4_CapData, seL4_CapRights,
seL4_CapTableObject, seL4_Word};
use ToCap;
cap_wrapper!{ ()
/// Fixed-length table for storing capabilities
CNode = seL4_CapTableObject |i| 16 * i,
}
/// An unforgeable marker on a capability.
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub struct Badge {
......@@ -20,11 +29,10 @@ pub struct Badge {
impl Badge {
pub fn new(val: u32) -> Badge {
// unsafe: mem: maybe use a Default::default() ?
let mut bits: seL4_CapData = unsafe { ::core::mem::zeroed() };
bits.set_Badge(val as seL4_Word);
Badge {
bits: bits
}
Badge { bits: bits }
}
pub fn get_value(&self) -> u32 {
......@@ -65,32 +73,36 @@ impl SlotRef {
/// Copy the capability in this slot into `dest`, inheriting `rights`.
#[inline(always)]
pub fn copy(&self, dest: SlotRef, rights: seL4_CapRights) -> ::Result {
errcheck!(seL4_CNode_Copy(dest.root.to_cap(),
unsafe_as_result!(seL4_CNode_Copy(
dest.root.to_cap(),
dest.cptr,
dest.depth,
self.root.to_cap(),
self.cptr,
self.depth,
rights))
rights,
))
}
/// Remove the capability in this slot, replacing it with the null capability.
#[inline(always)]
pub fn delete(&self) -> ::Result {
errcheck!(seL4_CNode_Delete(self.root.to_cap(), self.cptr, self.depth));
unsafe_as_result!(seL4_CNode_Delete(self.root.to_cap(), self.cptr, self.depth))
}
/// Copy the capability in this slot into `dest`, inheriting `rights` and applying `badge`.
#[inline(always)]
pub fn mint(&self, dest: SlotRef, rights: seL4_CapRights, badge: Badge) -> ::Result {
errcheck!(seL4_CNode_Mint(dest.root.to_cap(),
unsafe_as_result!(seL4_CNode_Mint(
dest.root.to_cap(),
dest.cptr,
dest.depth,
self.root.to_cap(),
self.cptr,
self.depth,
rights,
badge.bits));
badge.bits,
))
}
/// Move the capability in this slot into `dest`, clearing this slot.
......@@ -98,24 +110,28 @@ impl SlotRef {
/// Note: This is called `move_` because `move` is a keyword in Rust.
#[inline(always)]
pub fn move_(&self, dest: SlotRef) -> ::Result {
errcheck!(seL4_CNode_Move(dest.root.to_cap(),
unsafe_as_result!(seL4_CNode_Move(
dest.root.to_cap(),
dest.cptr,
dest.depth,
self.root.to_cap(),
self.cptr,
self.depth));
self.depth,
))
}
/// Move the capability in this slot into `dest`, applying `badge` and clearing this slot.
#[inline(always)]
pub fn mutate(&self, dest: SlotRef, badge: Badge) -> ::Result {
errcheck!(seL4_CNode_Mutate(dest.root.to_cap(),
unsafe_as_result!(seL4_CNode_Mutate(
dest.root.to_cap(),
dest.cptr,
dest.depth,
self.root.to_cap(),
self.cptr,
self.depth,
badge.bits));
badge.bits,
))
}
/// When used on a badged endpoint cap, cancel any outstanding send operations for that
......@@ -124,7 +140,7 @@ impl SlotRef {
/// This has no effect on other objects.
#[inline(always)]
pub fn cancel_badged_sends(&self) -> ::Result {
errcheck!(seL4_CNode_CancelBadgedSends(self.root.to_cap(), self.cptr, self.depth));
unsafe_as_result!(seL4_CNode_CancelBadgedSends(self.root.to_cap(), self.cptr, self.depth))
}
/// Delete all child capabilities of the capability in this slot.
......@@ -133,11 +149,12 @@ impl SlotRef {
///
/// - If the last cap to the TCB for the currently running thread is deleted, the thread will
/// be destroyed at that point and further child capabilities will not be deleted
///
/// - If the last cap to the memory storing this CNode is deleted, something bad happens and
/// the revoke will stop.
#[inline(always)]
pub fn revoke(&self) -> ::Result {
errcheck!(seL4_CNode_Revoke(self.root.to_cap(), self.cptr, self.depth));
unsafe_as_result!(seL4_CNode_Revoke(self.root.to_cap(), self.cptr, self.depth))
}
/// Atomically "rotate" the capability in `second` into `destination` applying
......@@ -146,15 +163,11 @@ impl SlotRef {
/// This is an associated function instead of a method because it's not really clear which slot
/// deserves to be the receiver.
#[inline(always)]
pub fn rotate(destination: SlotRef,
destination_badge: Badge,
pivot: SlotRef,
pivot_badge: Badge,
src: SlotRef)
pub fn rotate(dest: SlotRef, dest_badge: Badge, pivot: SlotRef,
pivot_badge: Badge, src: SlotRef)
-> ::Result {
let dest = destination;
let dest_badge = destination_badge;
errcheck!(seL4_CNode_Rotate(dest.root.to_cap(),
unsafe_as_result!(seL4_CNode_Rotate(
dest.root.to_cap(),
dest.cptr,
dest.depth,
dest_badge.bits,
......@@ -164,13 +177,14 @@ impl SlotRef {
pivot_badge.bits,
src.root.to_cap(),
src.cptr,
src.depth));
src.depth,
))
}
/// Save the reply capability into this slot.
#[inline(always)]
pub fn save_caller(&self) -> ::Result {
errcheck!(seL4_CNode_SaveCaller(self.root.to_cap(), self.cptr, self.depth));
unsafe_as_result!(seL4_CNode_SaveCaller(self.root.to_cap(), self.cptr, self.depth))
}
}
......@@ -222,7 +236,7 @@ impl CNodeInfo {
prefix: 0,
guard: 0,
radix: 0,
leftover: 0
leftover: 0,
};
let leftover_bits = ::core::mem::size_of::<seL4_Word>()
......@@ -230,7 +244,7 @@ impl CNodeInfo {
.wrapping_sub(self.prefix_bits as usize)
.wrapping_sub(self.guard_bits as usize)
.wrapping_sub(self.radix_bits as usize) as usize;
let one = 1 as seL4_Word; // makes type inference work.
let one: seL4_Word = 1;
decoded.leftover = cptr & one.wrapping_shl(leftover_bits as u32).wrapping_sub(1);
cptr = cptr.wrapping_shr(leftover_bits as u32);
......@@ -252,18 +266,15 @@ impl CNodeInfo {
.wrapping_sub(self.prefix_bits as usize)
.wrapping_sub(self.guard_bits as usize)
.wrapping_sub(self.radix_bits as usize) as usize;
let one = 1 as seL4_Word; // makes type inference work.
let one: seL4_Word = 1;
let mut result = decoded.prefix &
(one.wrapping_shl(self.prefix_bits as u32).wrapping_sub(1));
result = result.wrapping_shl(self.guard_bits as u32);
result |= decoded.guard &
(one.wrapping_shl(self.guard_bits as u32).wrapping_sub(1));
result |= decoded.guard & (one.wrapping_shl(self.guard_bits as u32).wrapping_sub(1));
result = result.wrapping_shl(self.radix_bits as u32);
result |= decoded.radix &
(one.wrapping_shl(self.radix_bits as u32).wrapping_sub(1));
result |= decoded.radix & (one.wrapping_shl(self.radix_bits as u32).wrapping_sub(1));
result = result.wrapping_shl(self.prefix_bits as u32);
result |= decoded.leftover &
(one.wrapping_shl(leftover_bits as u32).wrapping_sub(1));
result |= decoded.leftover & (one.wrapping_shl(leftover_bits as u32).wrapping_sub(1));
result
}
}
......@@ -291,7 +302,7 @@ impl Window {
let raw = DecodedCPtr {
prefix: self.cnode.cptr,
guard: info.guard_val,
radix: self.first_slot_idx.wrapping_add(i) as seL4_Word,
radix: self.first_slot_idx.wrapping_add(i),
leftover: 0,
};
......@@ -299,22 +310,14 @@ impl Window {
}
pub fn slotref_to(&self, info: &CNodeInfo, i: usize) -> Option<SlotRef> {
match self.cptr_to(info, i) {
Some(cptr) => {
Some(SlotRef {
self.cptr_to(info, i).map(|cptr| {
SlotRef {
root: self.cnode.root,
cptr: cptr,
depth: info.radix_bits
.wrapping_add(info.guard_bits)
.wrapping_add(info.prefix_bits)
})
},
None => None
.wrapping_add(info.prefix_bits),
}
})
}
}
cap_wrapper!{
#[doc = "Fixed-length table for storing capabilities"]
:CNode seL4_CapTableObject |i| 16*i
}
......@@ -9,9 +9,9 @@
//! Controlling the domain of threads.
cap_wrapper_inner!{
#[doc = "Authority to set domains"]
:DomainSet
cap_wrapper!{ ()
/// Authority to set domains
DomainSet,
}
impl DomainSet {
......
......@@ -32,9 +32,9 @@
use sel4_sys::*;
cap_wrapper!{
#[doc="An endpoint for message passing"]
:Endpoint seL4_EndpointObject |_| 16
cap_wrapper!{ ()
/// An endpoint for message passing
Endpoint = seL4_EndpointObject |_| 16,
}
/// The result of a successful receive.
......@@ -64,13 +64,16 @@ impl RecvToken {
///
/// Returns `Err` if the slice is not at least length `caps_unwrapped`.
pub fn get_unwrapped_caps(&self, caps: &mut [seL4_Word]) -> Result<(), ()> {
if caps.len() < seL4_MsgMaxExtraCaps && (caps.len() as seL4_Word) < self.caps_unwrapped {
if caps.len() < seL4_MsgMaxExtraCaps && caps.len() < self.caps_unwrapped {
return Err(());
}