simplify/cleanup code + bugfixes

- x86_64 seL4_TCBOject size is implemented

- ioapic level_triggered and active_low were incorrect
parent d35e18f7
Pipeline #464 canceled with stage
...@@ -19,11 +19,14 @@ pub trait ObjectAllocator { ...@@ -19,11 +19,14 @@ pub trait ObjectAllocator {
/// Otherwise, allocate a slot in this thread's CSpace. /// Otherwise, allocate a slot in this thread's CSpace.
fn allocate_slot(&self) -> Option<SlotRef>; fn allocate_slot(&self) -> Option<SlotRef>;
/// Mark a slot unused and available for allocation. /// Mark a slot unused and available for allocation.
fn free_slot(&self, slot: SlotRef) -> Result<(), Self::SlotFreeError>; fn free_slot(&self, slot: SlotRef) -> Result<(), Self::SlotFreeError>;
/// Allocate an object, storing the capability into the specified slot. /// Allocate an object, storing the capability into the specified slot.
fn allocate_object<T: Allocatable>(&self, dest: SlotRef) -> Result<Option<T>, Self::ObjectAllocError>; fn allocate_object<T: Allocatable>(&self, dest: SlotRef)
-> Result<Option<T>, Self::ObjectAllocError>;
/// Free an object, deleting it (thus removing it from the capability derivation tree) and /// Free an object, deleting it (thus removing it from the capability derivation tree) and
/// return the memory for use by the allocator. /// return the memory for use by the allocator.
fn free_object<T: Allocatable>(&self, obj: T) -> Result<(), Self::ObjectFreeError>; fn free_object<T: Allocatable>(&self, obj: T) -> Result<(), Self::ObjectFreeError>;
......
...@@ -8,28 +8,27 @@ ...@@ -8,28 +8,27 @@
// according to those terms. // according to those terms.
use sel4_sys::*; use sel4_sys::*;
use ToCap; use ToCap;
cap_wrapper_inner!{ cap_wrapper!{ ()
#[doc = "Authority to allocate ASID pools"] /// Authority to allocate ASID pools
:ASIDControl ASIDControl,
#[doc = "Authority to create page directories"] /// Authority to create page directories
:ASIDPool ASIDPool,
}
cap_wrapper!{ /// A 4K page of physical memory mapped into a page table
#[doc = "A 4K page of physical memory mapped into a page table"] SmallPage = seL4_ARM_SmallPageObject |_| 1 << 10,
:SmallPage seL4_ARM_SmallPageObject |_| 1 << 10 /// A 64K page of physical memory mapped into a page table
#[doc = "A 64K page of physical memory mapped into a page table"] LargePage = seL4_ARM_LargePageObject |_| 1 << 16,
:LargePage seL4_ARM_LargePageObject |_| 1 << 16 /// A 1M page of physical memory mapped into a page directory
#[doc = "A 1M page of physical memory mapped into a page directory"] Section = seL4_ARM_SectionObject |_| 1 << 20,
:Section seL4_ARM_SectionObject |_| 1 << 20 /// A 16M page of physical memory mapped into a page directory
#[doc = "A 16M page of physical memory mapped into a page directory"] SuperSection = seL4_ARM_SuperSectionObject |_| 1 << 24,
:SuperSection seL4_ARM_SuperSectionObject |_| 1 << 24 /// A page table, which can have pages mapped into it
#[doc = "A page table, which can have pages mapped into it"] PageTable = seL4_ARM_PageTableObject |_| 1 << 10,
:PageTable seL4_ARM_PageTableObject |_| 1 << 10 /// A page directory, which holds page tables or sections and forms the root of the vspace
#[doc = "A page directory, which holds page tables or sections and forms the root of the vspace"] PageDirectory = seL4_ARM_PageDirectoryObject |_| 1 << 14,
:PageDirectory seL4_ARM_PageDirectoryObject |_| 1 << 14
} }
impl ASIDControl { impl ASIDControl {
...@@ -39,7 +38,13 @@ impl ASIDControl { ...@@ -39,7 +38,13 @@ impl ASIDControl {
/// `untyped` must be 4KiB. /// `untyped` must be 4KiB.
#[inline(always)] #[inline(always)]
pub fn make_pool(&self, untyped: SmallPage, dest: ::SlotRef) -> ::Result { pub fn make_pool(&self, untyped: SmallPage, dest: ::SlotRef) -> ::Result {
errcheck!(seL4_ARM_ASIDControl_MakePool(self.cptr, untyped.to_cap(), dest.root.to_cap(), dest.cptr, dest.depth)); unsafe_as_result!(seL4_ARM_ASIDControl_MakePool(
self.cptr,
untyped.to_cap(),
dest.root.to_cap(),
dest.cptr,
dest.depth,
))
} }
} }
...@@ -47,7 +52,7 @@ impl ASIDPool { ...@@ -47,7 +52,7 @@ impl ASIDPool {
/// Assign a page directory to this ASID pool. /// Assign a page directory to this ASID pool.
#[inline(always)] #[inline(always)]
pub fn assign(&self, vroot: PageDirectory) -> ::Result { pub fn assign(&self, vroot: PageDirectory) -> ::Result {
errcheck!(seL4_ARM_ASIDPool_Assign(self.cptr, vroot.to_cap())); unsafe_as_result!(seL4_ARM_ASIDPool_Assign(self.cptr, vroot.to_cap()))
} }
} }
...@@ -56,20 +61,22 @@ macro_rules! page_impls { ...@@ -56,20 +61,22 @@ macro_rules! page_impls {
impl $name { impl $name {
/// Map this page into an address space. /// Map this page into an address space.
#[inline(always)] #[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights, attr: seL4_ARM_VMAttributes) -> ::Result { pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights,
errcheck!(seL4_ARM_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr)); attr: seL4_ARM_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_ARM_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr))
} }
/// Remap this page, possibly changing rights or attribute but not address. /// Remap this page, possibly changing rights or attribute but not address.
#[inline(always)] #[inline(always)]
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_ARM_VMAttributes) -> ::Result { pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights,
errcheck!(seL4_ARM_Page_Remap(self.cptr, pd.to_cap(), rights, attr)); attr: seL4_ARM_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_ARM_Page_Remap(self.cptr, pd.to_cap(), rights, attr))
} }
/// Unmap this page. /// Unmap this page.
#[inline(always)] #[inline(always)]
pub fn unmap(&self) -> ::Result { pub fn unmap(&self) -> ::Result {
errcheck!(seL4_ARM_Page_Unmap(self.cptr)); unsafe_as_result!(seL4_ARM_Page_Unmap(self.cptr))
} }
/// Get the physical address of the underlying frame. /// Get the physical address of the underlying frame.
...@@ -96,12 +103,12 @@ impl PageTable { ...@@ -96,12 +103,12 @@ impl PageTable {
/// Map this page table into an address space. /// Map this page table into an address space.
#[inline(always)] #[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, attr: seL4_ARM_VMAttributes) -> ::Result { pub fn map(&self, pd: PageDirectory, addr: seL4_Word, attr: seL4_ARM_VMAttributes) -> ::Result {
errcheck!(seL4_ARM_PageTable_Map(self.cptr, pd.to_cap(), addr, attr)); unsafe_as_result!(seL4_ARM_PageTable_Map(self.cptr, pd.to_cap(), addr, attr))
} }
/// Unmap this page. /// Unmap this page.
#[inline(always)] #[inline(always)]
pub fn unmap(&self) -> ::Result { pub fn unmap(&self) -> ::Result {
errcheck!(seL4_ARM_PageTable_Unmap(self.cptr)); unsafe_as_result!(seL4_ARM_PageTable_Unmap(self.cptr))
} }
} }
// Copyright (c) 2015 The Robigalia Project Developers
// Licensed under the Apache License, Version 2.0
// <LICENSE-APACHE or
// http://www.apache.org/licenses/LICENSE-2.0> or the MIT
// license <LICENSE-MIT or http://opensource.org/licenses/MIT>,
// at your option. All files in the project carrying such
// notice may not be copied, modified, or distributed except
// according to those terms.
#[cfg(target_arch = "x86")]
mod x86;
#[cfg(target_arch = "x86")]
pub use self::x86::*;
#[cfg(target_arch = "x86_64")]
mod x86_64;
#[cfg(target_arch = "x86_64")]
pub use self::x86_64::*;
#[cfg(all(target_arch = "arm", target_pointer_width = "32"))]
mod arm;
#[cfg(all(target_arch = "arm", target_pointer_width = "32"))]
pub use self::arm::*;
...@@ -8,29 +8,29 @@ ...@@ -8,29 +8,29 @@
// according to those terms. // according to those terms.
use sel4_sys::*; use sel4_sys::*;
use ToCap; use ToCap;
cap_wrapper_inner!{ cap_wrapper!{ ()
#[doc = "Authority to create ASID pools"] /// Authority to create ASID pools
:ASIDControl ASIDControl,
#[doc = "Authority to create page directories"] /// Authority to create page directories
:ASIDPool ASIDPool,
#[doc = "Authority to use port-IO"] /// Authority to use port-IO
:IOPort IOPort,
#[doc = "Authority to map IO page tables into a device's address space"] /// Authority to map IO page tables into a device's address space
:IOSpace IOSpace,
}
cap_wrapper!{ /// A page table for the IOMMU
#[doc = "A page table for the IOMMU"] IOPageTable = seL4_X86_IOPageTableObject |_| 1 << 10,
:IOPageTable seL4_X86_IOPageTableObject |_| 1 << 10 /// A page of physical memory that can be mapped into a vspace
#[doc = "A page of physical memory that can be mapped into a vspace"] Page = seL4_X86_4K |_| 1 << 10,
:Page seL4_X86_4K |_| 1 << 10 /// A 'large page' (4MiB) for use with PAE
#[doc = "A 'large page' (4MiB) for use with PAE"] LargePage = seL4_X86_LargePageObject |_| 1 << 22,
:LargePage seL4_X86_LargePageObject |_| 1 << 22 /// A page table, which can have pages mapped into it
#[doc = "A page table, which can have pages mapped into it"] PageTable = seL4_X86_PageTableObject |_| 1 << 10,
:PageTable seL4_X86_PageTableObject |_| 1 << 10 /// A page directory, which holds page tables and forms the root of the vspace
#[doc = "A page directory, which holds page tables and forms the root of the vspace"] PageDirectory = seL4_X86_PageDirectoryObject |_| 1 << 10,
:PageDirectory seL4_X86_PageDirectoryObject |_| 1 << 10
} }
impl ASIDControl { impl ASIDControl {
...@@ -40,7 +40,13 @@ impl ASIDControl { ...@@ -40,7 +40,13 @@ impl ASIDControl {
/// `untyped` must be 4KiB. /// `untyped` must be 4KiB.
#[inline(always)] #[inline(always)]
pub fn make_pool(&self, untyped: Page, dest: ::SlotRef) -> ::Result { pub fn make_pool(&self, untyped: Page, dest: ::SlotRef) -> ::Result {
errcheck!(seL4_X86_ASIDControl_MakePool(self.cptr, untyped.to_cap(), dest.root.to_cap(), dest.cptr, dest.depth)); unsafe_as_result!(seL4_X86_ASIDControl_MakePool(
self.cptr,
untyped.to_cap(),
dest.root.to_cap(),
dest.cptr,
dest.depth,
))
} }
} }
...@@ -48,7 +54,7 @@ impl ASIDPool { ...@@ -48,7 +54,7 @@ impl ASIDPool {
/// Assign a page directory to this ASID pool. /// Assign a page directory to this ASID pool.
#[inline(always)] #[inline(always)]
pub fn assign(&self, vroot: PageDirectory) -> ::Result { pub fn assign(&self, vroot: PageDirectory) -> ::Result {
errcheck!(seL4_X86_ASIDPool_Assign(self.cptr, vroot.to_cap())); unsafe_as_result!(seL4_X86_ASIDPool_Assign(self.cptr, vroot.to_cap()))
} }
} }
...@@ -89,19 +95,19 @@ impl IOPort { ...@@ -89,19 +95,19 @@ impl IOPort {
/// Write 8-bit `value` to the given port. /// Write 8-bit `value` to the given port.
#[inline(always)] #[inline(always)]
pub fn write8(&self, port: u16, value: u8) -> ::Result { pub fn write8(&self, port: u16, value: u8) -> ::Result {
errcheck!(seL4_X86_IOPort_Out8(self.cptr, port as seL4_Word, value as seL4_Word)); unsafe_as_result!(seL4_X86_IOPort_Out8(self.cptr, port as seL4_Word, value as seL4_Word))
} }
/// Write 16-bit `value` to the given port. /// Write 16-bit `value` to the given port.
#[inline(always)] #[inline(always)]
pub fn write16(&self, port: u16, value: u16) -> ::Result { pub fn write16(&self, port: u16, value: u16) -> ::Result {
errcheck!(seL4_X86_IOPort_Out16(self.cptr, port as seL4_Word, value as seL4_Word)); unsafe_as_result!(seL4_X86_IOPort_Out16(self.cptr, port as seL4_Word, value as seL4_Word))
} }
/// Write 32-bit `value` to the given port. /// Write 32-bit `value` to the given port.
#[inline(always)] #[inline(always)]
pub fn write32(&self, port: u16, value: u32) -> ::Result { pub fn write32(&self, port: u16, value: u32) -> ::Result {
errcheck!(seL4_X86_IOPort_Out32(self.cptr, port as seL4_Word, value as seL4_Word)); unsafe_as_result!(seL4_X86_IOPort_Out32(self.cptr, port as seL4_Word, value as seL4_Word))
} }
} }
...@@ -109,7 +115,7 @@ impl IOPageTable { ...@@ -109,7 +115,7 @@ impl IOPageTable {
/// Map this page table into an IOSpace at `addr` /// Map this page table into an IOSpace at `addr`
#[inline(always)] #[inline(always)]
pub fn map(&self, iospace: IOSpace, addr: seL4_Word) -> ::Result { pub fn map(&self, iospace: IOSpace, addr: seL4_Word) -> ::Result {
errcheck!(seL4_X86_IOPageTable_Map(self.cptr, iospace.to_cap(), addr)); unsafe_as_result!(seL4_X86_IOPageTable_Map(self.cptr, iospace.to_cap(), addr))
} }
} }
...@@ -118,25 +124,27 @@ impl Page { ...@@ -118,25 +124,27 @@ impl Page {
/// Map this page into an IOSpace with `rights` at `addr`. /// Map this page into an IOSpace with `rights` at `addr`.
#[inline(always)] #[inline(always)]
pub fn map_io(&self, iospace: IOSpace, rights: seL4_CapRights, addr: seL4_Word) -> ::Result { pub fn map_io(&self, iospace: IOSpace, rights: seL4_CapRights, addr: seL4_Word) -> ::Result {
errcheck!(seL4_X86_Page_MapIO(self.cptr, iospace.to_cap(), rights, addr)); unsafe_as_result!(seL4_X86_Page_MapIO(self.cptr, iospace.to_cap(), rights, addr))
} }
/// Map this page into an address space. /// Map this page into an address space.
#[inline(always)] #[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights, attr: seL4_X86_VMAttributes) -> ::Result { pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights,
errcheck!(seL4_X86_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr)); attr: seL4_X86_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_X86_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr))
} }
/// Remap this page, possibly changing rights or attribute but not address. /// Remap this page, possibly changing rights or attribute but not address.
#[inline(always)] #[inline(always)]
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_X86_VMAttributes) -> ::Result { pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_X86_VMAttributes)
errcheck!(seL4_X86_Page_Remap(self.cptr, pd.to_cap(), rights, attr)); -> ::Result {
unsafe_as_result!(seL4_X86_Page_Remap(self.cptr, pd.to_cap(), rights, attr))
} }
/// Unmap this page. /// Unmap this page.
#[inline(always)] #[inline(always)]
pub fn unmap(&self) -> ::Result { pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_Page_Unmap(self.cptr)); unsafe_as_result!(seL4_X86_Page_Unmap(self.cptr))
} }
/// Get the physical address of the underlying frame. /// Get the physical address of the underlying frame.
...@@ -157,13 +165,13 @@ impl PageTable { ...@@ -157,13 +165,13 @@ impl PageTable {
/// Map this page table into an address space. /// Map this page table into an address space.
#[inline(always)] #[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, attr: seL4_X86_VMAttributes) -> ::Result { pub fn map(&self, pd: PageDirectory, addr: seL4_Word, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_PageTable_Map(self.cptr, pd.to_cap(), addr, attr)); unsafe_as_result!(seL4_X86_PageTable_Map(self.cptr, pd.to_cap(), addr, attr))
} }
/// Unmap this page. /// Unmap this page.
#[inline(always)] #[inline(always)]
pub fn unmap(&self) -> ::Result { pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_PageTable_Unmap(self.cptr)); unsafe_as_result!(seL4_X86_PageTable_Unmap(self.cptr))
} }
} }
...@@ -173,7 +181,7 @@ impl PageDirectory { ...@@ -173,7 +181,7 @@ impl PageDirectory {
/// Returns (accessed, dirty). /// Returns (accessed, dirty).
#[inline(always)] #[inline(always)]
pub fn get_status(&self, vaddr: usize) -> Result<(bool, bool), ::Error> { pub fn get_status(&self, vaddr: usize) -> Result<(bool, bool), ::Error> {
let res = unsafe { seL4_X86_PageDirectory_GetStatusBits(self.cptr, vaddr as seL4_Word) }; let res = unsafe { seL4_X86_PageDirectory_GetStatusBits(self.cptr, vaddr) };
if res.error == 0 { if res.error == 0 {
unsafe { unsafe {
let buf = seL4_GetIPCBuffer(); let buf = seL4_GetIPCBuffer();
...@@ -196,8 +204,19 @@ impl ::irq::IRQControl { ...@@ -196,8 +204,19 @@ impl ::irq::IRQControl {
/// ///
/// `vector` is the CPU vector the interrupt will be delivered to. /// `vector` is the CPU vector the interrupt will be delivered to.
#[inline(always)] #[inline(always)]
pub fn get_msi(&self, slotref: ::SlotRef, pci_bus: seL4_Word, pci_dev: seL4_Word, pci_func: seL4_Word, handle: seL4_Word, vector: seL4_Word) -> ::Result { pub fn get_msi(&self, slotref: ::SlotRef, pci_bus: seL4_Word, pci_dev: seL4_Word,
errcheck!(seL4_IRQControl_GetMSI(self.to_cap(), slotref.root.to_cap(), slotref.cptr, slotref.depth as seL4_Word, pci_bus, pci_dev, pci_func, handle, vector)); pci_func: seL4_Word, handle: seL4_Word, vector: seL4_Word) -> ::Result {
unsafe_as_result!(seL4_IRQControl_GetMSI(
self.to_cap(),
slotref.root.to_cap(),
slotref.cptr,
slotref.depth as seL4_Word,
pci_bus,
pci_dev,
pci_func,
handle,
vector,
))
} }
/// Create an IRQHandler capability for an interrupt from an IOAPIC. /// Create an IRQHandler capability for an interrupt from an IOAPIC.
...@@ -212,7 +231,19 @@ impl ::irq::IRQControl { ...@@ -212,7 +231,19 @@ impl ::irq::IRQControl {
/// ///
/// `vector` is the CPU vector the interrupt will be delivered on. /// `vector` is the CPU vector the interrupt will be delivered on.
#[inline(always)] #[inline(always)]
pub fn get_ioapic(&self, slotref: ::SlotRef, ioapic: seL4_Word, pin: seL4_Word, level_triggered: bool, active_low: bool, vector: seL4_Word) -> ::Result { pub fn get_ioapic(&self, slotref: ::SlotRef, ioapic: seL4_Word, pin: seL4_Word,
errcheck!(seL4_IRQControl_GetIOAPIC(self.to_cap(), slotref.root.to_cap(), slotref.cptr, slotref.depth as seL4_Word, ioapic, pin, if level_triggered { 0 } else { 1 }, if active_low { 0 } else { 1 }, vector)); level_triggered: bool, active_low: bool, vector: seL4_Word)
-> ::Result {
unsafe_as_result!(seL4_IRQControl_GetIOAPIC(
self.to_cap(),
slotref.root.to_cap(),
slotref.cptr,
slotref.depth as seL4_Word,
ioapic,
pin,
level_triggered as usize,
active_low as usize,
vector,
))
} }
} }
This diff is collapsed.
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...@@ -9,9 +9,9 @@ ...@@ -9,9 +9,9 @@
//! Controlling the domain of threads. //! Controlling the domain of threads.
cap_wrapper_inner!{ cap_wrapper!{ ()
#[doc = "Authority to set domains"] /// Authority to set domains
:DomainSet DomainSet,
} }
impl DomainSet { impl DomainSet {
......
...@@ -32,9 +32,9 @@ ...@@ -32,9 +32,9 @@
use sel4_sys::*; use sel4_sys::*;
cap_wrapper!{ cap_wrapper!{ ()
#[doc="An endpoint for message passing"] /// An endpoint for message passing
:Endpoint seL4_EndpointObject |_| 16 Endpoint = seL4_EndpointObject |_| 16,
} }
/// The result of a successful receive. /// The result of a successful receive.
...@@ -64,13 +64,16 @@ impl RecvToken { ...@@ -64,13 +64,16 @@ impl RecvToken {
/// ///
/// Returns `Err` if the slice is not at least length `caps_unwrapped`. /// Returns `Err` if the slice is not at least length `caps_unwrapped`.
pub fn get_unwrapped_caps(&self, caps: &mut [seL4_Word]) -> Result<(), ()> { pub fn get_unwrapped_caps(&self, caps: &mut [seL4_Word]) -> Result<(), ()> {
if caps.len() < seL4_MsgMaxExtraCaps && (caps.len() as seL4_Word) < self.caps_unwrapped { if caps.len() < seL4_MsgMaxExtraCaps && caps.len() < self.caps_unwrapped {
return Err(()); return Err(());
} }
unsafe { unsafe {
::core::intrinsics::copy_nonoverlapping(&(*seL4_GetIPCBuffer()).caps_or_badges as *const seL4_Word, ::core::intrinsics::copy_nonoverlapping(
caps.as_mut_ptr(), self.caps_unwrapped as usize) &(*seL4_GetIPCBuffer()).caps_or_badges as *const seL4_Word,
caps.as_mut_ptr(),
self.caps_unwrapped as usize,
)
} }
Ok(()) Ok(())
...@@ -80,14 +83,15 @@ impl RecvToken { ...@@ -80,14 +83,15 @@ impl RecvToken {
/// ///
/// Returns `Err` if the slice is not at least length `words_transferred`. /// Returns `Err` if the slice is not at least length `words_transferred`.
pub fn get_data(&self, data: &mut [seL4_Word]) -> Result<(), ()> { pub fn get_data(&self, data: &mut [seL4_Word]) -> Result<(), ()> {
if data.len() < seL4_MsgMaxLength && (data.len() as seL4_Word) < self.len { if data.len() < seL4_MsgMaxLength && data.len() < self.len {
return Err(()); return Err(());
} }
unsafe { unsafe {
::core::intrinsics::copy_nonoverlapping(&(*seL4_GetIPCBuffer()).msg as *const seL4_Word, ::core::intrinsics::copy_nonoverlapping(
data.as_mut_ptr(), &(*seL4_GetIPCBuffer()).msg as *const seL4_Word, data.as_mut_ptr(),
self.len as usize) self.len as usize,
)
} }
Ok(()) Ok(())
...@@ -133,22 +137,19 @@ impl Endpoint { ...@@ -133,22 +137,19 @@ impl Endpoint {
} }
unsafe { unsafe {
let buf = seL4_GetIPCBuffer(); let buf = seL4_GetIPCBuffer();
::core::ptr::copy_nonoverlapping(data.as_ptr(), ::core::ptr::copy_nonoverlapping(
(&mut (*buf).msg).as_mut_ptr(), data.as_ptr(),
data.len()); (&mut (*buf).msg).as_mut_ptr(),
::core::ptr::copy_nonoverlapping(caps.as_ptr(), data.len(),
(&mut (*buf).caps_or_badges).as_mut_ptr(), );
caps.len()); ::core::ptr::copy_nonoverlapping(
seL4_Send(self.cptr, caps.as_ptr(),
seL4_MessageInfo::new(0, (&mut (*buf).caps_or_badges).as_mut_ptr(),
0, caps.len()
caps.len() as seL4_Word, );
data.len() as seL4_Word)); seL4_Send(self.cptr, seL4_MessageInfo::new(0, 0, caps.len(), data.len()));
if (*buf).tag.get_label() != 0 { unsafe_as_result!(@ (*buf).tag.get_label())
return Err(::Error(::GoOn::CheckIPCBuf));
}
} }
Ok(())
} }
/// Raw send, using data already in the IPC buffer /// Raw send, using data already in the IPC buffer
...@@ -157,11 +158,8 @@ impl Endpoint { ...@@ -157,11 +158,8 @@ impl Endpoint {
unsafe { unsafe {
let buf = seL4_GetIPCBuffer(); let buf = seL4_GetIPCBuffer();
seL4_Send(self.cptr, seL4_MessageInfo::new(0, 0, caps, data)); seL4_Send(self.cptr, seL4_MessageInfo::new(0, 0, caps, data));
if (*buf).tag.get_label() != 0 { unsafe_as_result!(@ (*buf).tag.get_label())
return Err(::Error(::GoOn::CheckIPCBuf));
}
} }
Ok(())
} }
/// Raw non-blocking send, using data already in the IPC buffer /// Raw non-blocking send, using data already in the IPC buffer
...@@ -170,11 +168,8 @@ impl Endpoint { ...@@ -170,11 +168,8 @@ impl Endpoint {
unsafe { unsafe {
let buf = seL4_GetIPCBuffer(); let buf = seL4_GetIPCBuffer();
seL4_NBSend(self.cptr, seL4_MessageInfo::new(0, 0, caps, data)); seL4_NBSend(self.cptr, seL4_MessageInfo::new(0, 0, caps, data));
if (*buf).tag.get_label() != 0 { unsafe_as_result!(@ (*buf).tag.get_label())
return Err(::Error(::GoOn::CheckIPCBuf));
}
} }
Ok(())
} }
/// Try to send a message, returning no indication of failure if the message could not be sent. /// Try to send a message, returning no indication of failure if the message could not be sent.
...@@ -188,22 +183,19 @@ impl Endpoint { ...@@ -188,22 +183,19 @@ impl Endpoint {
} }
unsafe { unsafe {
let buf = seL4_GetIPCBuffer();