simplify/cleanup code + bugfixes

- x86_64 seL4_TCBOject size is implemented

- ioapic level_triggered and active_low were incorrect
parent d35e18f7
Pipeline #464 canceled with stage
......@@ -19,11 +19,14 @@ pub trait ObjectAllocator {
/// Otherwise, allocate a slot in this thread's CSpace.
fn allocate_slot(&self) -> Option<SlotRef>;
/// Mark a slot unused and available for allocation.
fn free_slot(&self, slot: SlotRef) -> Result<(), Self::SlotFreeError>;
/// Allocate an object, storing the capability into the specified slot.
fn allocate_object<T: Allocatable>(&self, dest: SlotRef) -> Result<Option<T>, Self::ObjectAllocError>;
fn allocate_object<T: Allocatable>(&self, dest: SlotRef)
-> Result<Option<T>, Self::ObjectAllocError>;
/// Free an object, deleting it (thus removing it from the capability derivation tree) and
/// return the memory for use by the allocator.
fn free_object<T: Allocatable>(&self, obj: T) -> Result<(), Self::ObjectFreeError>;
......
......@@ -8,28 +8,27 @@
// according to those terms.
use sel4_sys::*;
use ToCap;
cap_wrapper_inner!{
#[doc = "Authority to allocate ASID pools"]
:ASIDControl
#[doc = "Authority to create page directories"]
:ASIDPool
}
cap_wrapper!{ ()
/// Authority to allocate ASID pools
ASIDControl,
/// Authority to create page directories
ASIDPool,
cap_wrapper!{
#[doc = "A 4K page of physical memory mapped into a page table"]
:SmallPage seL4_ARM_SmallPageObject |_| 1 << 10
#[doc = "A 64K page of physical memory mapped into a page table"]
:LargePage seL4_ARM_LargePageObject |_| 1 << 16
#[doc = "A 1M page of physical memory mapped into a page directory"]
:Section seL4_ARM_SectionObject |_| 1 << 20
#[doc = "A 16M page of physical memory mapped into a page directory"]
:SuperSection seL4_ARM_SuperSectionObject |_| 1 << 24
#[doc = "A page table, which can have pages mapped into it"]
:PageTable seL4_ARM_PageTableObject |_| 1 << 10
#[doc = "A page directory, which holds page tables or sections and forms the root of the vspace"]
:PageDirectory seL4_ARM_PageDirectoryObject |_| 1 << 14
/// A 4K page of physical memory mapped into a page table
SmallPage = seL4_ARM_SmallPageObject |_| 1 << 10,
/// A 64K page of physical memory mapped into a page table
LargePage = seL4_ARM_LargePageObject |_| 1 << 16,
/// A 1M page of physical memory mapped into a page directory
Section = seL4_ARM_SectionObject |_| 1 << 20,
/// A 16M page of physical memory mapped into a page directory
SuperSection = seL4_ARM_SuperSectionObject |_| 1 << 24,
/// A page table, which can have pages mapped into it
PageTable = seL4_ARM_PageTableObject |_| 1 << 10,
/// A page directory, which holds page tables or sections and forms the root of the vspace
PageDirectory = seL4_ARM_PageDirectoryObject |_| 1 << 14,
}
impl ASIDControl {
......@@ -39,7 +38,13 @@ impl ASIDControl {
/// `untyped` must be 4KiB.
#[inline(always)]
pub fn make_pool(&self, untyped: SmallPage, dest: ::SlotRef) -> ::Result {
errcheck!(seL4_ARM_ASIDControl_MakePool(self.cptr, untyped.to_cap(), dest.root.to_cap(), dest.cptr, dest.depth));
unsafe_as_result!(seL4_ARM_ASIDControl_MakePool(
self.cptr,
untyped.to_cap(),
dest.root.to_cap(),
dest.cptr,
dest.depth,
))
}
}
......@@ -47,7 +52,7 @@ impl ASIDPool {
/// Assign a page directory to this ASID pool.
#[inline(always)]
pub fn assign(&self, vroot: PageDirectory) -> ::Result {
errcheck!(seL4_ARM_ASIDPool_Assign(self.cptr, vroot.to_cap()));
unsafe_as_result!(seL4_ARM_ASIDPool_Assign(self.cptr, vroot.to_cap()))
}
}
......@@ -56,20 +61,22 @@ macro_rules! page_impls {
impl $name {
/// Map this page into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights, attr: seL4_ARM_VMAttributes) -> ::Result {
errcheck!(seL4_ARM_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr));
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights,
attr: seL4_ARM_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_ARM_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr))
}
/// Remap this page, possibly changing rights or attribute but not address.
#[inline(always)]
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_ARM_VMAttributes) -> ::Result {
errcheck!(seL4_ARM_Page_Remap(self.cptr, pd.to_cap(), rights, attr));
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights,
attr: seL4_ARM_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_ARM_Page_Remap(self.cptr, pd.to_cap(), rights, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_ARM_Page_Unmap(self.cptr));
unsafe_as_result!(seL4_ARM_Page_Unmap(self.cptr))
}
/// Get the physical address of the underlying frame.
......@@ -96,12 +103,12 @@ impl PageTable {
/// Map this page table into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, attr: seL4_ARM_VMAttributes) -> ::Result {
errcheck!(seL4_ARM_PageTable_Map(self.cptr, pd.to_cap(), addr, attr));
unsafe_as_result!(seL4_ARM_PageTable_Map(self.cptr, pd.to_cap(), addr, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_ARM_PageTable_Unmap(self.cptr));
unsafe_as_result!(seL4_ARM_PageTable_Unmap(self.cptr))
}
}
// Copyright (c) 2015 The Robigalia Project Developers
// Licensed under the Apache License, Version 2.0
// <LICENSE-APACHE or
// http://www.apache.org/licenses/LICENSE-2.0> or the MIT
// license <LICENSE-MIT or http://opensource.org/licenses/MIT>,
// at your option. All files in the project carrying such
// notice may not be copied, modified, or distributed except
// according to those terms.
#[cfg(target_arch = "x86")]
mod x86;
#[cfg(target_arch = "x86")]
pub use self::x86::*;
#[cfg(target_arch = "x86_64")]
mod x86_64;
#[cfg(target_arch = "x86_64")]
pub use self::x86_64::*;
#[cfg(all(target_arch = "arm", target_pointer_width = "32"))]
mod arm;
#[cfg(all(target_arch = "arm", target_pointer_width = "32"))]
pub use self::arm::*;
......@@ -8,29 +8,29 @@
// according to those terms.
use sel4_sys::*;
use ToCap;
cap_wrapper_inner!{
#[doc = "Authority to create ASID pools"]
:ASIDControl
#[doc = "Authority to create page directories"]
:ASIDPool
#[doc = "Authority to use port-IO"]
:IOPort
#[doc = "Authority to map IO page tables into a device's address space"]
:IOSpace
}
cap_wrapper!{
#[doc = "A page table for the IOMMU"]
:IOPageTable seL4_X86_IOPageTableObject |_| 1 << 10
#[doc = "A page of physical memory that can be mapped into a vspace"]
:Page seL4_X86_4K |_| 1 << 10
#[doc = "A 'large page' (4MiB) for use with PAE"]
:LargePage seL4_X86_LargePageObject |_| 1 << 22
#[doc = "A page table, which can have pages mapped into it"]
:PageTable seL4_X86_PageTableObject |_| 1 << 10
#[doc = "A page directory, which holds page tables and forms the root of the vspace"]
:PageDirectory seL4_X86_PageDirectoryObject |_| 1 << 10
cap_wrapper!{ ()
/// Authority to create ASID pools
ASIDControl,
/// Authority to create page directories
ASIDPool,
/// Authority to use port-IO
IOPort,
/// Authority to map IO page tables into a device's address space
IOSpace,
/// A page table for the IOMMU
IOPageTable = seL4_X86_IOPageTableObject |_| 1 << 10,
/// A page of physical memory that can be mapped into a vspace
Page = seL4_X86_4K |_| 1 << 10,
/// A 'large page' (4MiB) for use with PAE
LargePage = seL4_X86_LargePageObject |_| 1 << 22,
/// A page table, which can have pages mapped into it
PageTable = seL4_X86_PageTableObject |_| 1 << 10,
/// A page directory, which holds page tables and forms the root of the vspace
PageDirectory = seL4_X86_PageDirectoryObject |_| 1 << 10,
}
impl ASIDControl {
......@@ -40,7 +40,13 @@ impl ASIDControl {
/// `untyped` must be 4KiB.
#[inline(always)]
pub fn make_pool(&self, untyped: Page, dest: ::SlotRef) -> ::Result {
errcheck!(seL4_X86_ASIDControl_MakePool(self.cptr, untyped.to_cap(), dest.root.to_cap(), dest.cptr, dest.depth));
unsafe_as_result!(seL4_X86_ASIDControl_MakePool(
self.cptr,
untyped.to_cap(),
dest.root.to_cap(),
dest.cptr,
dest.depth,
))
}
}
......@@ -48,7 +54,7 @@ impl ASIDPool {
/// Assign a page directory to this ASID pool.
#[inline(always)]
pub fn assign(&self, vroot: PageDirectory) -> ::Result {
errcheck!(seL4_X86_ASIDPool_Assign(self.cptr, vroot.to_cap()));
unsafe_as_result!(seL4_X86_ASIDPool_Assign(self.cptr, vroot.to_cap()))
}
}
......@@ -89,19 +95,19 @@ impl IOPort {
/// Write 8-bit `value` to the given port.
#[inline(always)]
pub fn write8(&self, port: u16, value: u8) -> ::Result {
errcheck!(seL4_X86_IOPort_Out8(self.cptr, port as seL4_Word, value as seL4_Word));
unsafe_as_result!(seL4_X86_IOPort_Out8(self.cptr, port as seL4_Word, value as seL4_Word))
}
/// Write 16-bit `value` to the given port.
#[inline(always)]
pub fn write16(&self, port: u16, value: u16) -> ::Result {
errcheck!(seL4_X86_IOPort_Out16(self.cptr, port as seL4_Word, value as seL4_Word));
unsafe_as_result!(seL4_X86_IOPort_Out16(self.cptr, port as seL4_Word, value as seL4_Word))
}
/// Write 32-bit `value` to the given port.
#[inline(always)]
pub fn write32(&self, port: u16, value: u32) -> ::Result {
errcheck!(seL4_X86_IOPort_Out32(self.cptr, port as seL4_Word, value as seL4_Word));
unsafe_as_result!(seL4_X86_IOPort_Out32(self.cptr, port as seL4_Word, value as seL4_Word))
}
}
......@@ -109,7 +115,7 @@ impl IOPageTable {
/// Map this page table into an IOSpace at `addr`
#[inline(always)]
pub fn map(&self, iospace: IOSpace, addr: seL4_Word) -> ::Result {
errcheck!(seL4_X86_IOPageTable_Map(self.cptr, iospace.to_cap(), addr));
unsafe_as_result!(seL4_X86_IOPageTable_Map(self.cptr, iospace.to_cap(), addr))
}
}
......@@ -118,25 +124,27 @@ impl Page {
/// Map this page into an IOSpace with `rights` at `addr`.
#[inline(always)]
pub fn map_io(&self, iospace: IOSpace, rights: seL4_CapRights, addr: seL4_Word) -> ::Result {
errcheck!(seL4_X86_Page_MapIO(self.cptr, iospace.to_cap(), rights, addr));
unsafe_as_result!(seL4_X86_Page_MapIO(self.cptr, iospace.to_cap(), rights, addr))
}
/// Map this page into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr));
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights,
attr: seL4_X86_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_X86_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr))
}
/// Remap this page, possibly changing rights or attribute but not address.
#[inline(always)]
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_Page_Remap(self.cptr, pd.to_cap(), rights, attr));
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_X86_VMAttributes)
-> ::Result {
unsafe_as_result!(seL4_X86_Page_Remap(self.cptr, pd.to_cap(), rights, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_Page_Unmap(self.cptr));
unsafe_as_result!(seL4_X86_Page_Unmap(self.cptr))
}
/// Get the physical address of the underlying frame.
......@@ -157,13 +165,13 @@ impl PageTable {
/// Map this page table into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_PageTable_Map(self.cptr, pd.to_cap(), addr, attr));
unsafe_as_result!(seL4_X86_PageTable_Map(self.cptr, pd.to_cap(), addr, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_PageTable_Unmap(self.cptr));
unsafe_as_result!(seL4_X86_PageTable_Unmap(self.cptr))
}
}
......@@ -173,7 +181,7 @@ impl PageDirectory {
/// Returns (accessed, dirty).
#[inline(always)]
pub fn get_status(&self, vaddr: usize) -> Result<(bool, bool), ::Error> {
let res = unsafe { seL4_X86_PageDirectory_GetStatusBits(self.cptr, vaddr as seL4_Word) };
let res = unsafe { seL4_X86_PageDirectory_GetStatusBits(self.cptr, vaddr) };
if res.error == 0 {
unsafe {
let buf = seL4_GetIPCBuffer();
......@@ -196,8 +204,19 @@ impl ::irq::IRQControl {
///
/// `vector` is the CPU vector the interrupt will be delivered to.
#[inline(always)]
pub fn get_msi(&self, slotref: ::SlotRef, pci_bus: seL4_Word, pci_dev: seL4_Word, pci_func: seL4_Word, handle: seL4_Word, vector: seL4_Word) -> ::Result {
errcheck!(seL4_IRQControl_GetMSI(self.to_cap(), slotref.root.to_cap(), slotref.cptr, slotref.depth as seL4_Word, pci_bus, pci_dev, pci_func, handle, vector));
pub fn get_msi(&self, slotref: ::SlotRef, pci_bus: seL4_Word, pci_dev: seL4_Word,
pci_func: seL4_Word, handle: seL4_Word, vector: seL4_Word) -> ::Result {
unsafe_as_result!(seL4_IRQControl_GetMSI(
self.to_cap(),
slotref.root.to_cap(),
slotref.cptr,
slotref.depth as seL4_Word,
pci_bus,
pci_dev,
pci_func,
handle,
vector,
))
}
/// Create an IRQHandler capability for an interrupt from an IOAPIC.
......@@ -212,7 +231,19 @@ impl ::irq::IRQControl {
///
/// `vector` is the CPU vector the interrupt will be delivered on.
#[inline(always)]
pub fn get_ioapic(&self, slotref: ::SlotRef, ioapic: seL4_Word, pin: seL4_Word, level_triggered: bool, active_low: bool, vector: seL4_Word) -> ::Result {
errcheck!(seL4_IRQControl_GetIOAPIC(self.to_cap(), slotref.root.to_cap(), slotref.cptr, slotref.depth as seL4_Word, ioapic, pin, if level_triggered { 0 } else { 1 }, if active_low { 0 } else { 1 }, vector));
pub fn get_ioapic(&self, slotref: ::SlotRef, ioapic: seL4_Word, pin: seL4_Word,
level_triggered: bool, active_low: bool, vector: seL4_Word)
-> ::Result {
unsafe_as_result!(seL4_IRQControl_GetIOAPIC(
self.to_cap(),
slotref.root.to_cap(),
slotref.cptr,
slotref.depth as seL4_Word,
ioapic,
pin,
level_triggered as usize,
active_low as usize,
vector,
))
}
}
......@@ -8,46 +8,45 @@
// according to those terms.
use sel4_sys::*;
use ToCap;
cap_wrapper_inner!{
#[doc = "Authority to create ASID pools"]
:ASIDControl
#[doc = "Authority to create page directories"]
:ASIDPool
#[doc = "Authority to use port-IO"]
:IOPort
#[doc = "Authority to map IO page tables into a device's address space"]
:IOSpace
}
cap_wrapper!{ ()
/// Authority to create ASID pools
ASIDControl,
/// Authority to create page directories
ASIDPool,
/// Authority to use port-IO
IOPort,
/// Authority to map IO page tables into a device's address space
IOSpace,
cap_wrapper!{
#[doc = "A page directory pointer table, which holds page directories"]
:PDPT seL4_X86_PDPTObject |_| 1 << seL4_PDPTBits
#[doc = "A page map level 4, which holds PDPTs"]
:PML4 seL4_X64_PML4Object |_| 1 << seL4_PML4Bits
#[doc = "A huge (1G) page of physical memory that can be mapped into a vspace"]
:HugePage seL4_X86_4K |_| 1 << seL4_HugePageBits
#[doc = "A (4K) page of physical memory that can be mapped into a vspace"]
:Page seL4_X86_4K |_| 1 << seL4_PageBits
#[doc = "A large (2M) page of physical memory that can be mapped into a vspace"]
:LargePage seL4_X86_LargePageObject |_| 1 << seL4_LargePageBits
#[doc = "A page table, which can have pages mapped into it"]
:PageTable seL4_X86_PageTableObject |_| 1 << seL4_PageTableBits
#[doc = "A page directory, which holds page tables"]
:PageDirectory seL4_X86_PageDirectoryObject |_| 1 << seL4_PageDirBits
#[doc = "A page table for the IOMMU"]
:IOPageTable seL4_X86_IOPageTableObject |_| 1 << seL4_IOPageTableBits
#[doc = "A virtual CPU, for virtualization"]
:VCPU seL4_X86_VCPUObject |_| 1 << seL4_VCPUBits
#[doc = "Extended page table (virt) PML4"]
:EPTPML4 seL4_X86_EPTPML4Object |_| 1 << seL4_EPTPML4Bits
#[doc = "Extended page table (virt) PDPT"]
:EPTPDPT seL4_X86_EPTPDPTObject |_| 1 << seL4_EPTPDPTBits
#[doc = "Extended page table (virt) PageDirectory"]
:EPTPageDirectory seL4_X86_EPTPDObject |_| 1 << seL4_EPTPDBits
#[doc = "Extended page table (virt) PageTable"]
:EPTPageTable seL4_X86_EPTPTObject |_| 1 << seL4_EPTPTBits
/// A page directory pointer table, which holds page directories
PDPT = seL4_X86_PDPTObject |_| 1 << seL4_PDPTBits,
/// A page map level 4, which holds PDPTs
PML4 = seL4_X64_PML4Object |_| 1 << seL4_PML4Bits,
/// A huge (1G) page of physical memory that can be mapped into a vspace
HugePage = seL4_X86_4K |_| 1 << seL4_HugePageBits,
/// A (4K) page of physical memory that can be mapped into a vspace
Page = seL4_X86_4K |_| 1 << seL4_PageBits,
/// A large (2M) page of physical memory that can be mapped into a vspace
LargePage = seL4_X86_LargePageObject |_| 1 << seL4_LargePageBits,
/// A page table, which can have pages mapped into it
PageTable = seL4_X86_PageTableObject |_| 1 << seL4_PageTableBits,
/// A page directory, which holds page tables
PageDirectory = seL4_X86_PageDirectoryObject |_| 1 << seL4_PageDirBits,
/// A page table for the IOMMU
IOPageTable = seL4_X86_IOPageTableObject |_| 1 << seL4_IOPageTableBits,
/// A virtual CPU, for virtualization
VCPU = seL4_X86_VCPUObject |_| 1 << seL4_VCPUBits,
/// Extended page table (virt) PML4
EPTPML4 = seL4_X86_EPTPML4Object |_| 1 << seL4_EPTPML4Bits,
/// Extended page table (virt) PDPT
EPTPDPT = seL4_X86_EPTPDPTObject |_| 1 << seL4_EPTPDPTBits,
/// Extended page table (virt) PageDirectory
EPTPageDirectory = seL4_X86_EPTPDObject |_| 1 << seL4_EPTPDBits,
/// Extended page table (virt) PageTable
EPTPageTable = seL4_X86_EPTPTObject |_| 1 << seL4_EPTPTBits,
}
impl ASIDControl {
......@@ -57,7 +56,13 @@ impl ASIDControl {
/// `untyped` must be 4KiB.
#[inline(always)]
pub fn make_pool(&self, untyped: Page, dest: ::SlotRef) -> ::Result {
errcheck!(seL4_X86_ASIDControl_MakePool(self.cptr, untyped.to_cap(), dest.root.to_cap(), dest.cptr, dest.depth));
unsafe_as_result!(seL4_X86_ASIDControl_MakePool(
self.cptr,
untyped.to_cap(),
dest.root.to_cap(),
dest.cptr,
dest.depth,
))
}
}
......@@ -65,7 +70,7 @@ impl ASIDPool {
/// Assign a page directory to this ASID pool.
#[inline(always)]
pub fn assign(&self, vroot: PageDirectory) -> ::Result {
errcheck!(seL4_X86_ASIDPool_Assign(self.cptr, vroot.to_cap()));
unsafe_as_result!(seL4_X86_ASIDPool_Assign(self.cptr, vroot.to_cap()))
}
}
......@@ -106,19 +111,19 @@ impl IOPort {
/// Write 8-bit `value` to the given port.
#[inline(always)]
pub fn write8(&self, port: u16, value: u8) -> ::Result {
errcheck!(seL4_X86_IOPort_Out8(self.cptr, port as seL4_Word, value as seL4_Word));
unsafe_as_result!(seL4_X86_IOPort_Out8(self.cptr, port as seL4_Word, value as seL4_Word))
}
/// Write 16-bit `value` to the given port.
#[inline(always)]
pub fn write16(&self, port: u16, value: u16) -> ::Result {
errcheck!(seL4_X86_IOPort_Out16(self.cptr, port as seL4_Word, value as seL4_Word));
unsafe_as_result!(seL4_X86_IOPort_Out16(self.cptr, port as seL4_Word, value as seL4_Word))
}
/// Write 32-bit `value` to the given port.
#[inline(always)]
pub fn write32(&self, port: u16, value: u32) -> ::Result {
errcheck!(seL4_X86_IOPort_Out32(self.cptr, port as seL4_Word, value as seL4_Word));
unsafe_as_result!(seL4_X86_IOPort_Out32(self.cptr, port as seL4_Word, value as seL4_Word))
}
}
......@@ -126,7 +131,7 @@ impl IOPageTable {
/// Map this page table into an IOSpace at `addr`
#[inline(always)]
pub fn map(&self, iospace: IOSpace, addr: seL4_Word) -> ::Result {
errcheck!(seL4_X86_IOPageTable_Map(self.cptr, iospace.to_cap(), addr));
unsafe_as_result!(seL4_X86_IOPageTable_Map(self.cptr, iospace.to_cap(), addr))
}
}
......@@ -135,25 +140,27 @@ impl Page {
/// Map this page into an IOSpace with `rights` at `addr`.
#[inline(always)]
pub fn map_io(&self, iospace: IOSpace, rights: seL4_CapRights, addr: seL4_Word) -> ::Result {
errcheck!(seL4_X86_Page_MapIO(self.cptr, iospace.to_cap(), rights, addr));
unsafe_as_result!(seL4_X86_Page_MapIO(self.cptr, iospace.to_cap(), rights, addr))
}
/// Map this page into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr));
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, rights: seL4_CapRights,
attr: seL4_X86_VMAttributes) -> ::Result {
unsafe_as_result!(seL4_X86_Page_Map(self.cptr, pd.to_cap(), addr, rights, attr))
}
/// Remap this page, possibly changing rights or attribute but not address.
#[inline(always)]
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_Page_Remap(self.cptr, pd.to_cap(), rights, attr));
pub fn remap(&self, pd: PageDirectory, rights: seL4_CapRights, attr: seL4_X86_VMAttributes)
-> ::Result {
unsafe_as_result!(seL4_X86_Page_Remap(self.cptr, pd.to_cap(), rights, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_Page_Unmap(self.cptr));
unsafe_as_result!(seL4_X86_Page_Unmap(self.cptr))
}
/// Get the physical address of the underlying frame.
......@@ -172,13 +179,13 @@ impl PageTable {
/// Map this page table into an address space.
#[inline(always)]
pub fn map(&self, pd: PageDirectory, addr: seL4_Word, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_PageTable_Map(self.cptr, pd.to_cap(), addr, attr));
unsafe_as_result!(seL4_X86_PageTable_Map(self.cptr, pd.to_cap(), addr, attr))
}
/// Unmap this page.
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_PageTable_Unmap(self.cptr));
unsafe_as_result!(seL4_X86_PageTable_Unmap(self.cptr))
}
}
......@@ -188,7 +195,7 @@ impl PageDirectory {
/// Returns (accessed, dirty).
#[inline(always)]
pub fn get_status(&self, vaddr: usize) -> Result<(bool, bool), ::Error> {
let res = unsafe { seL4_X86_PageDirectory_GetStatusBits(self.cptr, vaddr as seL4_Word) };
let res = unsafe { seL4_X86_PageDirectory_GetStatusBits(self.cptr, vaddr) };
if res.error == 0 {
unsafe {
let buf = seL4_GetIPCBuffer();
......@@ -204,12 +211,12 @@ impl PageDirectory {
/// Map this page directory into a PDPT
#[inline(always)]
pub fn map(&self, pdpt: PDPT, addr: seL4_Word, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_PageDirectory_Map(self.cptr, pdpt.to_cap(), addr, attr));
unsafe_as_result!(seL4_X86_PageDirectory_Map(self.cptr, pdpt.to_cap(), addr, attr))
}
/// Unmap this page directory from the PDPT it is mapped into
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_PageDirectory_Unmap(self.cptr));
unsafe_as_result!(seL4_X86_PageDirectory_Unmap(self.cptr))
}
}
......@@ -217,13 +224,13 @@ impl PDPT {
/// Map this PDPT into a PML4
#[inline(always)]
pub fn map(&self, pml4: PML4, addr: seL4_Word, attr: seL4_X86_VMAttributes) -> ::Result {
errcheck!(seL4_X86_PDPT_Map(self.cptr, pml4.to_cap(), addr, attr));
unsafe_as_result!(seL4_X86_PDPT_Map(self.cptr, pml4.to_cap(), addr, attr))
}
/// Unmap this PDPT from the PML4 it is mapped into
#[inline(always)]
pub fn unmap(&self) -> ::Result {
errcheck!(seL4_X86_PDPT_Unmap(self.cptr));
unsafe_as_result!(seL4_X86_PDPT_Unmap(self.cptr))
}
}
......@@ -236,8 +243,19 @@ impl ::irq::IRQControl {
///
/// `vector` is the CPU vector the interrupt will be delivered to.
#[inline(always)]
pub fn get_msi(&self, slotref: ::SlotRef, pci_bus: seL4_Word, pci_dev: seL4_Word, pci_func: seL4_Word, handle: seL4_Word, vector: seL4_Word) -> ::Result {
errcheck!(seL4_IRQControl_GetMSI(self.to_cap(), slotref.root.to_cap(), slotref.cptr, slotref.depth as seL4_Word, pci_bus, pci_dev, pci_func, handle, vector));
pub fn get_msi(&self, slotref: ::SlotRef, pci_bus: seL4_Word, pci_dev: seL4_Word,
pci_func: seL4_Word, handle: seL4_Word, vector: seL4_Word) -> ::Result {
unsafe_as_result!(seL4_IRQControl_GetMSI(
self.to_cap(),
slotref.root.to_cap(),
slotref.cptr,
slotref.depth as seL4_Word,
pci_bus,
pci_dev,
pci_func,
handle,
vector,
))
}
/// Create an IRQHandler capability for an interrupt from an IOAPIC.
......@@ -252,7 +270,19 @@ impl ::irq::IRQControl {
///
/// `vector` is the CPU vector the interrupt will be delivered on.
#[inline(always)]
pub fn get_ioapic(&self, slotref: ::SlotRef, ioapic: seL4_Word, pin: seL4_Word, level_triggered: bool, active_low: bool, vector: seL4_Word) -> ::Result {
errcheck!(seL4_IRQControl_GetIOAPIC(self.to_cap(), slotref.root.to_cap(), slotref.cptr, slotref.depth as seL4_Word, ioapic, pin, if level_triggered { 0 } else { 1 }, if active_low { 0 } else { 1 }, vector));
pub fn get_ioapic(&self, slotref: ::SlotRef, ioapic: seL4_Word, pin: seL4_Word,
level_triggered: bool, active_low: bool, vector: seL4_Word)
-> ::Result {
unsafe_as_result!(seL4_IRQControl_GetIOAPIC(
self.to_cap(),
slotref.root.to_cap(),
slotref.cptr,
slotref.depth as seL4_Word,
ioapic,
pin,
level_triggered as usize,
active_low as usize,
vector,